Fiducial

AI agents hallucinate pinouts. fiducial catches them.

The observation that started this: LLMs write plausible schematics with real bugs — label typos that split nets, pins wired to nothing, wrong symbols, missing debug headers. And the standard tools don’t catch it, because ERC/DRC check rules, not intent.

In the benchmark, an AI-authored RP2040 devboard passed ERC completely clean while its crystal caps were silently disconnected — the board would never boot. fiducial’s intent audit caught it in seconds:

ref     pin    expected          actual            result
*U1     20     /XIN              Net-(U1-XIN)      WRONG
58/64 connections verified

The workflow

The core insight is declaring intent before wiring:

1. Write intent as intent.csv (ref,pin,expected_net) from the datasheet — before the schematic exists.
2. Let the agent author the schematic using the instruction library in skills/.
3. Prove it: lint → erc → check-intent. Exit codes are agent gates.
4. Then layout: drc → render → inspect.

python fiducial/scripts/fiducial.py lint myboard.kicad_sch          # structure
python fiducial/scripts/fiducial.py erc myboard.kicad_sch            # ERC
python fiducial/scripts/fiducial.py check-intent myboard.kicad_sch intent.csv  # intent

Zero dependencies on purpose

The verification tools run on the Python stdlib only — no pydantic, no click. That matters because the whole point is to be a drop-in submodule: git submodule add, run bootstrap.sh, and any agent that reads AGENTS.md gets the hardware-design skillset. KiCad 7+ is the only external requirement, and most diagnostics work even without kicad-cli.

What it catches

• lint — duplicate refs, single-use labels, orphan nets, missing libs, off-grid
• check-intent — any pin on the wrong net, NC handling
• check-rules — house-style rules.csv (min-contacts, net-exclusive)
• overlap-check — silent shorts (wires sharing coordinates)

Plus a grid-aware SchematicBuilder that generates lint-clean schematics programmatically.

Status

v0 — builder + schematic-side verification battle-tested on an RP2040 devboard; PCB-side drc/render works but isn’t yet regression-covered. Next domains on the roadmap: mechanical CAD, using the same verification architecture.